A Low Cost VLSI Architecture for Spike Sorting Based on Feature Extraction with Peak Search
The goal of this paper is to present a novel VLSI architecture for spike sorting with high classification accuracy, low area costs and low power consumption. A novel feature extraction algorithm with low computational complexities is proposed for the design of the architecture. In the feature extrac...
保存先:
| 主要な著者: | , , |
|---|---|
| フォーマット: | Artigo |
| 言語: | Inglês |
| 出版事項: |
MDPI AG
2016-12-01
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| シリーズ: | Sensors |
| 主題: | |
| オンライン･アクセス: | http://www.mdpi.com/1424-8220/16/12/2084 |
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