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ECC Memory for Fault Tolerant RISC-V Processors
Numerous processor cores based on the popular RISC-V Instruction Set Architecture have been developed in the past few years and are freely available. The same applies for RISC-V ecosystems that allow to implement System-on-Chips with RISC-V processors on ASICs or FPGAs. However, so far only very lit...
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| Publicado no: | Architecture of Computing Systems – ARCS 2020 |
|---|---|
| Main Authors: | , , , , , |
| Formato: | Artigo |
| Idioma: | Inglês |
| Publicado em: |
2020
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| Assuntos: | |
| Acesso em linha: | https://ncbi.nlm.nih.gov/pmc/articles/PMC7343426/ https://ncbi.nlm.nih.govhttp://dx.doi.org/10.1007/978-3-030-52794-5_4 |
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