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Process Optimization of Via Plug Multilevel Interconnections in CMOS Logic Devices
This paper reports on the optimization of the device and wiring in a via structure applied to multilevel metallization (MLM) used in CMOS logic devices. A MLM via can be applied to the Tungsten (W) plug process of the logic device by following the most optimized barrier deposition scheme of RF etchi...
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| Izdano u: | Micromachines (Basel) |
|---|---|
| Glavni autori: | , , , |
| Format: | Artigo |
| Jezik: | Inglês |
| Izdano: |
MDPI
2019
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| Teme: | |
| Online pristup: | https://ncbi.nlm.nih.gov/pmc/articles/PMC7019522/ https://ncbi.nlm.nih.gov/pubmed/31881782 https://ncbi.nlm.nih.govhttp://dx.doi.org/10.3390/mi11010032 |
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