ロード中...
The Optimization of Spacer Engineering for Capacitor-Less DRAM Based on the Dual-Gate Tunneling Transistor
The DRAM based on the dual-gate tunneling FET (DGTFET) has the advantages of capacitor-less structure and high retention time. In this paper, the optimization of spacer engineering for DGTFET DRAM is systematically investigated by Silvaco-Atlas tool to further improve its performance, including the...
保存先:
| 出版年: | Nanoscale Res Lett |
|---|---|
| 主要な著者: | , , , , |
| フォーマット: | Artigo |
| 言語: | Inglês |
| 出版事項: |
Springer US
2018
|
| 主題: | |
| オンライン･アクセス: | https://ncbi.nlm.nih.gov/pmc/articles/PMC5838025/ https://ncbi.nlm.nih.gov/pubmed/29508093 https://ncbi.nlm.nih.govhttp://dx.doi.org/10.1186/s11671-018-2483-8 |
| タグ: |
タグ追加
タグなし, このレコードへの初めてのタグを付けませんか!
|