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Logical optimization of Boolean nets using Shannon expansion
A synthesis of logical circuits, comprising functional combination blocks of very large scale integration circuits, is one of the most important tasks of computer-aided design. As the data size of design tasks increases, the execution time of synthesis of logic circuits also increases. The global te...
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| Main Authors: | , |
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| Formato: | Artigo |
| Idioma: | Russo |
| Publicado em: |
The United Institute of Informatics Problems of the National Academy of Sciences of Belarus
2019-06-01
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| Colecção: | Informatika |
| Assuntos: | |
| Acesso em linha: | https://inf.grid.by/jour/article/view/658 |
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