A 12-bit High-Speed Time-Interleaved Pipelined Asynchronous Successive-Approximation ADC in 22-nm FDSOI CMOS
A 12-bit time-interleaved (TI) analog-to-digital converter (ADC) with pipelined successive-approximation (SAR) channels is presented in this paper. The ADC consists of four TI channels, each incorporating a two-stage pipelined asynchronous SAR ADC. To facilitate clock distribution, a common bootstra...
Sábháilte in:
| Príomhchruthaitheoirí: | , , |
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| Formáid: | Artigo |
| Teanga: | Inglês |
| Foilsithe / Cruthaithe: |
IEEE
2024-01-01
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| Sraith: | IEEE Access |
| Ábhair: | |
| Rochtain ar líne: | https://ieeexplore.ieee.org/document/10477955/ |
| Clibeanna: |
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