A 12-bit High-Speed Time-Interleaved Pipelined Asynchronous Successive-Approximation ADC in 22-nm FDSOI CMOS
A 12-bit time-interleaved (TI) analog-to-digital converter (ADC) with pipelined successive-approximation (SAR) channels is presented in this paper. The ADC consists of four TI channels, each incorporating a two-stage pipelined asynchronous SAR ADC. To facilitate clock distribution, a common bootstra...
Сохранить в:
| Главные авторы: | , , |
|---|---|
| Формат: | Artigo |
| Язык: | Inglês |
| Опубликовано: |
IEEE
2024-01-01
|
| Серии: | IEEE Access |
| Предметы: | |
| Online-ссылка: | https://ieeexplore.ieee.org/document/10477955/ |
| Метки: |
Нет меток, Требуется 1-ая метка записи!
|