LDPC Decoder of High Speed Multi-Rate DVB-S2 Based on FPGA
A multi-rate LDPC decoder architecture for DVB-S2 codes based on FPGA is proposed. Through elementary transformation on the parity check matrices of DVB-S2 LDPC codes, a new matrix whose left is a QC sub-matrix and right is Transformation of Staircase lower triangular (TST) sub-matrix is obtained. T...
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| Natura: | Artigo |
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| Lingua: | Chinês |
| Pubblicazione: |
EDP Sciences
2019-04-01
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| Serie: | Xibei Gongye Daxue Xuebao |
| Soggetti: | |
| Accesso online: | https://www.jnwpu.org/articles/jnwpu/full_html/2019/02/jnwpu2019372p299/jnwpu2019372p299.html |
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