A Hybrid Technique Based on ECC and Hardened Cells for Tolerating Random Multiple-Bit Upsets in SRAM Arrays
MBU is an increasing challenge in SRAM memory, due to the chip’s large area of SRAM, and supply power scaling applied to reduce static consumption. Powerful ECCs can cope with random MBUs, but at the expense of complex encoding/decoding circuits, and high memory redundancy. Alternatively, rad...
Αποθηκεύτηκε σε:
| Κύριοι συγγραφείς: | , , , , |
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| Μορφή: | Artigo |
| Γλώσσα: | Inglês |
| Έκδοση: |
IEEE
2024-01-01
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| Σειρά: | IEEE Access |
| Θέματα: | |
| Διαθέσιμο Online: | https://ieeexplore.ieee.org/document/10534066/ |
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