Fully Integrated GaN-on-Silicon Power-Rail ESD Clamp Circuit Without Transient Leakage Current During Normal Power-on Operation
When more circuit functions are integrated into a single chip fabricated by the GaN-on-Silicon process, the need for on-chip electrostatic discharge (ESD) protection design becomes crucial to safeguard GaN integrated circuits (ICs). In this work, the power-rail ESD clamp circuit with gate-coupled de...
Wedi'i Gadw mewn:
| Prif Awduron: | , |
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| Fformat: | Artigo |
| Iaith: | Inglês |
| Cyhoeddwyd: |
IEEE
2024-01-01
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| Cyfres: | IEEE Journal of the Electron Devices Society |
| Pynciau: | |
| Mynediad Ar-lein: | https://ieeexplore.ieee.org/document/10681588/ |
| Tagiau: |
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