A Design and Characterization of CMOS SPAD Fabricated in a 0.18-<italic>&#x03BC;</italic>m Standard Process

This article presents the design and characterization of a cost-effective single-photon avalanche diode (SPAD) implemented using a standard 180-nm CMOS process without any process modification. Proposed SPAD employs a p+/n-well junction as the multiplication region and realized in two main structure...

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Auteurs principaux:	Woojin Jo, Hyun-Seung Choi, Byungchoul Park
Format:	Artigo
Langue:	Inglês
Publié:	IEEE 2025-01-01
Collection:	IEEE Access
Sujets:	CMOS photodetector cost-effective SPAD low-noise photon detection single-photon avalanche diode (SPAD) time-resolved imaging
Accès en ligne:	https://ieeexplore.ieee.org/document/11261539/
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