A 13.2-fJ/Step 74.3-dB SNDR Pipelined Noise-Shaping SAR+VCO ADC
This work presents an OTA-free pipelined passive noise-shaping successive approximation register (NS-SAR) + VCO ADC that offers high resolution (>12-bit) with only a 5-bit NS-SAR stage and <inline-formula> <tex-math notation="LaTeX">$4\times $ </tex-math></inline-formula>–<inline-formu...
I tiakina i:
| Ngā kaituhi matua: | , |
|---|---|
| Hōputu: | Artigo |
| Reo: | Inglês |
| I whakaputaina: |
IEEE
2025-01-01
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| Rangatū: | IEEE Open Journal of the Solid-State Circuits Society |
| Ngā marau: | |
| Urunga tuihono: | https://ieeexplore.ieee.org/document/10816503/ |
| Ngā Tūtohu: |
Kāore He Tūtohu, Me noho koe te mea tuatahi ki te tūtohu i tēnei pūkete!
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