Test environment for verification of multi-processor memory subsystem unit
State of the art microprocessor systems usually include complex hierarchy of a cache memory. Coherence protocols are used to maintain memory consistency. An implementation of memory subsystem in HDL (hardware description language) is complex and error-prone task. Ensuring the correct functioning of...
I tiakina i:
| Ngā kaituhi matua: | , |
|---|---|
| Hōputu: | Artigo |
| Reo: | Inglês |
| I whakaputaina: |
Russian Academy of Sciences, Ivannikov Institute for System Programming
2019-09-01
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| Rangatū: | Труды Института системного программирования РАН |
| Ngā marau: | |
| Urunga tuihono: | https://ispranproceedings.elpub.ru/jour/article/view/1180 |
| Ngā Tūtohu: |
Kāore He Tūtohu, Me noho koe te mea tuatahi ki te tūtohu i tēnei pūkete!
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