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VLSI implementation of AES algorithm against differential power attack and differential fault attack

A VLSI implementation of AES algorithm against both differential power attack and differential fault attack was proposed. The main countermeasures employed in this hardware design are masking technique and two-dimensional parity-based concurrent error detection method. And exploits such methods as s...

Ausführliche Beschreibung

Gespeichert in:
Hauptverfasser: HAN Jun, ZENG Xiao-yang, ZHAO Jia
Format: Artigo
Sprache:Chinês
Veröffentlicht: Editorial Department of Journal on Communications 2010-01-01
Schriftenreihe:Tongxin xuebao
Schlagworte:
information security
anti-attack algorithm
VLSI implementation
side channel attack
AES
Online-Zugang:http://www.joconline.com.cn/zh/article/74650743/
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