Towards Area Efficient Logic Circuit: Exploring Potential of Reconfigurable Gate by Generic Exact Synthesis
In this article, we propose a generic design methodology to achieve area-efficient reconfigurable logic circuits by using exact synthesis based on Boolean satisfiability (SAT) solver. The proposed methodology better leverages the high representation ability of emerging reconfigurable logic gates (RL...
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| Principais autores: | , , |
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| Formato: | Artigo |
| Idioma: | Inglês |
| Publicado em: |
IEEE
2023-01-01
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| coleção: | IEEE Open Journal of the Computer Society |
| Assuntos: | |
| Acesso em linha: | https://ieeexplore.ieee.org/document/10059178/ |
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