Dual‐Modulated Vertically Stacked Transistors With Fully Laminated Plate‐Type Architecture Featuring Nanoscale Channel Length

ABSTRACT A transistor with fully laminated plate‐type triode electrodes, source, drain and gate offers higher current density than a typical transistor design by allowing a 2D current path. Nanoscale transistors face challenges like off‐state leakage, so we introduce a new design using a laminated p...

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Principais autores:	Goeun Pyo, Su Jin Heo, Jeonggyun Jang, Hongki Kang, Byeongmoon Lee, Hyuk‐Jun Kwon, Jae Eun Jang
פורמט:	Artigo
שפה:	Inglês
יצא לאור:	Wiley 2026-04-01
סדרה:	Advanced Science
נושאים:	dual gate transistors dual modulation graphene transistors nanoscale channel length vertically stacked transistors vertical thin film transistors
גישה מקוונת:	https://doi.org/10.1002/advs.202519410
תגים:	הוספת תג אין תגיות, היה/י הראשונ/ה לתייג את הרשומה!