Hardware Reduction for Lut–Based Mealy FSMs
A method is proposed targeting a decrease in the number of LUTs in circuits of FPGA-based Mealy FSMs. The method improves hardware consumption for Mealy FSMs with the encoding of collections of output variables. The approach is based on constructing a partition for the set of internal states. Each s...
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| Autors principals: | , , |
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| Format: | Artigo |
| Idioma: | Inglês |
| Publicat: |
Sciendo
2018-09-01
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| Col·lecció: | International Journal of Applied Mathematics and Computer Science |
| Matèries: | |
| Accés en línia: | https://doi.org/10.2478/amcs-2018-0046 |
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