A Scalable Formal Framework for the Verification and Vulnerability Analysis of Redundancy-Based Error-Resilient Null Convention Logic Asynchronous Circuits

The increasing demand for high-speed, energy-efficient, and miniaturized electronics has led to significant challenges and compromises in the domain of conventional clock-based digital designs, most notably reduced circuit reliability, particularly in mission-critical hardware. At scaled technology...

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Номзүйн дэлгэрэнгүй

Үндсэн зохиолчид:	Dipayan Mazumder, Mithun Datta, Alexander C. Bodoh, Ashiq A. Sakib
Формат:	Artigo
Хэл сонгох:	Inglês
Хэвлэсэн:	MDPI AG 2024-01-01
Цуврал:	Journal of Low Power Electronics and Applications
Нөхцлүүд:	asynchronous logic quasi-delay insensitive (QDI) null convention logic (NCL) error resilience design validation
Онлайн хандалт:	https://www.mdpi.com/2079-9268/14/1/5
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