A Scalable Formal Framework for the Verification and Vulnerability Analysis of Redundancy-Based Error-Resilient Null Convention Logic Asynchronous Circuits
The increasing demand for high-speed, energy-efficient, and miniaturized electronics has led to significant challenges and compromises in the domain of conventional clock-based digital designs, most notably reduced circuit reliability, particularly in mission-critical hardware. At scaled technology...
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| Autori principali: | , , , |
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| Natura: | Artigo |
| Lingua: | Inglês |
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MDPI AG
2024-01-01
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| Serie: | Journal of Low Power Electronics and Applications |
| Soggetti: | |
| Accesso online: | https://www.mdpi.com/2079-9268/14/1/5 |
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