Clustered Page Table Compression for TLB Coalescing
The support for virtual memory is a key aspect of modern system on a chip (SoC). Traditional address translation schemes rely on a single translation lookaside buffer (TLB) entry to translate a virtual page to a physical page. To improve the TLB utilization, various TLB coalescing schemes merge mult...
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| Hoofdauteurs: | , |
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| Formaat: | Artigo |
| Taal: | Inglês |
| Gepubliceerd in: |
IEEE
2026-01-01
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| Reeks: | IEEE Access |
| Onderwerpen: | |
| Online toegang: | https://ieeexplore.ieee.org/document/11366650/ |
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