An Efficient QC-LDPC Decoder Architecture for 5G-NR Wireless Communication Standards Targeting FPGA

This novel research introduces a game-changing architecture design for Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) decoders in Fifth-Generation New-Radio (5G-NR) wireless communications, specifically designed to meet precise specifications and leveraging the layered Min-Sum (MS) algorithm. Our i...

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Autores principales:	Bilal Mejmaa, Malika Alami Marktani, Ismail Akharraz, Abdelaziz Ahaitouf
Formato:	Artigo
Lenguaje:	Inglês
Publicado:	MDPI AG 2024-08-01
Colección:	Computers
Materias:	wireless communication 5G-NR standards LDPC codes min-sum algorithm HDL Verifier co-design
Acceso en línea:	https://www.mdpi.com/2073-431X/13/8/195
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