An Efficient QC-LDPC Decoder Architecture for 5G-NR Wireless Communication Standards Targeting FPGA
This novel research introduces a game-changing architecture design for Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) decoders in Fifth-Generation New-Radio (5G-NR) wireless communications, specifically designed to meet precise specifications and leveraging the layered Min-Sum (MS) algorithm. Our i...
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| Autori principali: | , , , |
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| Natura: | Artigo |
| Lingua: | Inglês |
| Pubblicazione: |
MDPI AG
2024-08-01
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| Serie: | Computers |
| Soggetti: | |
| Accesso online: | https://www.mdpi.com/2073-431X/13/8/195 |
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