Risky Translations: Securing TLBs against Timing Side Channels
Microarchitectural side-channel vulnerabilities in modern processors are known to be a powerful attack vector that can be utilized to bypass common security boundaries like memory isolation. As shown by recent variants of transient execution attacks related to Spectre and Meltdown, those side chann...
Na minha lista:
| Principais autores: | , , , |
|---|---|
| Formato: | Artigo |
| Idioma: | Inglês |
| Publicado em: |
Ruhr-Universität Bochum
2022-11-01
|
| coleção: | Transactions on Cryptographic Hardware and Embedded Systems |
| Assuntos: | |
| Acesso em linha: | https://tches.iacr.org/index.php/TCHES/article/view/9945 |
| Tags: |
Sem tags, seja o primeiro a adicionar uma tag!
|