Fast iterative circuits and RAM-based mergers to accelerate data sort in software/hardware systems; pp. 323–335

The paper suggests and describes two architectures for parallel data sort. The ï¬rst architecture is applicable to large data sets and it combines three stages of data processing: data sorting in hardware (in a Field-Programmable Gate Arrays â FPGA), merging preliminary sorted blocks in hardware (in...

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Principais autores:	Valery Sklyarov, Iouliia Skliarova, Artjom Rjabov, Alexander Sudnitson
格式:	Artigo
語言:	Inglês
出版:	Estonian Academy Publishers 2017-06-01
叢編:	Proceedings of the Estonian Academy of Sciences
主題:	parallel data processing merging iterative networks communication-time processing field-programmable gate array (fpga) peripheral component interconnect (pci)expressbus.
在線閱讀:	https://kirj.ee/public/proceedings_pdf/2017/issue_3/proc-2017-3-323-335.pdf
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