Fast iterative circuits and RAM-based mergers to accelerate data sort in software/hardware systems; pp. 323–335

The paper suggests and describes two architectures for parallel data sort. The ï¬rst architecture is applicable to large data sets and it combines three stages of data processing: data sorting in hardware (in a Field-Programmable Gate Arrays â FPGA), merging preliminary sorted blocks in hardware (in...

תיאור מלא

מידע ביבליוגרפי

Principais autores:	Valery Sklyarov, Iouliia Skliarova, Artjom Rjabov, Alexander Sudnitson
פורמט:	Artigo
שפה:	Inglês
יצא לאור:	Estonian Academy Publishers 2017-06-01
סדרה:	Proceedings of the Estonian Academy of Sciences
נושאים:	parallel data processing merging iterative networks communication-time processing field-programmable gate array (fpga) peripheral component interconnect (pci)expressbus.
גישה מקוונת:	https://kirj.ee/public/proceedings_pdf/2017/issue_3/proc-2017-3-323-335.pdf
תגים:	הוספת תג אין תגיות, היה/י הראשונ/ה לתייג את הרשומה!