Hybrid Digital/Analog Predistorter Architecture With Enhanced Robustness to Hardware Impairments
In this paper, a hybrid predistortion architecture that allies the benefits of digital and analog predistortion techniques is investigated. This Hybrid Digital/Analog Predistorter (H-DAPD) uses a low order memory polynomial as a baseband digital predistortion function. To alleviate the complexity of...
保存先:
| 主要な著者: | , |
|---|---|
| フォーマット: | Artigo |
| 言語: | Inglês |
| 出版事項: |
IEEE
2024-01-01
|
| シリーズ: | IEEE Access |
| 主題: | |
| オンライン･アクセス: | https://ieeexplore.ieee.org/document/10636135/ |
| タグ: |
タグなし, このレコードへの初めてのタグを付けませんか!
|