Efficient Implementation of SPEEDY Block Cipher on Cortex-M3 and RISC-V Microcontrollers
The SPEEDY block cipher family announced at the CHES 2021 shows excellent performance on hardware architectures. Due to the nature of the hardware-friendly design of SPEEDY, the algorithm has low performance for software implementations. In particular, 6-bit S-box and bit permutation operations of S...
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| Principais autores: | , , , |
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| Formato: | Artigo |
| Idioma: | Inglês |
| Publicado: |
MDPI AG
2022-11-01
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| Series: | Mathematics |
| Assuntos: | |
| Acceso en liña: | https://www.mdpi.com/2227-7390/10/22/4236 |
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