Negative Design Margin Realization through Deep Path Activity Detection Combined with Dynamic Voltage Scaling in a 55 nm Near-Threshold 32-Bit Microcontroller

This paper presents an innovative approach for predicting timing errors tailored to near-/sub-threshold operations, addressing the energy-efficient requirements of digital circuits in applications, such as IoT devices and wearables. The method involves assessing deep path activity within an adjustab...

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Hlavní autoři:	Run-Ze Yu, Zhen-Hao Li, Xi Deng, Zheng-Lin Liu
Médium:	Artigo
Jazyk:	Inglês
Vydáno:	MDPI AG 2023-08-01
Edice:	Sensors
Témata:	dynamic voltage scaling (DVS) negative design margin error detection and correction (EDaC) ultra-low voltage near-threshold operation high stability
On-line přístup:	https://www.mdpi.com/1424-8220/23/17/7498
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