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Design of a Sub-Picosecond Jitter with Adjustable-Range CMOS Delay-Locked Loop for High-Speed and Low-Power Applications

A Delay-Locked Loop (DLL) with a modified charge pump circuit is proposed for generating high-resolution linear delay steps with sub-picosecond jitter performance and adjustable delay range. The small-signal model of the modified charge pump circuit is analyzed to bring forth the relationship betwee...

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Detalhes bibliográficos
Publicado no:Sensors (Basel)
Main Authors: Abdulrazzaq, Bilal I., Ibrahim, Omar J., Kawahito, Shoji, Sidek, Roslina M., Shafie, Suhaidi, Yunus, Nurul Amziah Md., Lee, Lini, Halin, Izhal Abdul
Formato: Artigo
Idioma:Inglês
Publicado em: MDPI 2016
Assuntos:
Acesso em linha:https://ncbi.nlm.nih.gov/pmc/articles/PMC5087382/
https://ncbi.nlm.nih.gov/pubmed/27690040
https://ncbi.nlm.nih.govhttp://dx.doi.org/10.3390/s16101593
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