Kim, S., Choi, S., Hwang, W. S., & Cho, B. J. (2016). Valley-engineered ultra-thin silicon for high-performance junctionless transistors. Sci Rep.
Chicago Style CitationKim, Seung-Yoon, Sung-Yool Choi, Wan Sik Hwang, i Byung Jin Cho. "Valley-engineered Ultra-thin Silicon for High-performance Junctionless Transistors." Sci Rep 2016.
Cita MLAKim, Seung-Yoon, Sung-Yool Choi, Wan Sik Hwang, i Byung Jin Cho. "Valley-engineered Ultra-thin Silicon for High-performance Junctionless Transistors." Sci Rep 2016.
Atenció: Aquestes cites poden no estar 100% correctes.