A CMOS ASIC Design for SiPM Arrays

Our lab has previously reported on novel board-level readout electronics for an 8×8 silicon photomultiplier (SiPM) array featuring row/column summation technique to reduce the hardware requirements for signal processing. We are taking the next step by implementing a monolithic CMOS chip which is bas...

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Autori principali: Dey, Samrat, Banks, Lushon, Chen, Shaw-Pin, Xu, Wenbin, Lewellen, Thomas K., Miyaoka, Robert S., Rudell, Jacques C.
Natura: Artigo
Lingua:Inglês
Pubblicazione: 2011
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Article
Accesso online:https://ncbi.nlm.nih.gov/pmc/articles/PMC4016969/
https://ncbi.nlm.nih.gov/pubmed/24825923
https://ncbi.nlm.nih.govhttp://dx.doi.org/10.1109/NSSMIC.2011.6154092
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