Efficacy of Transistor Interleaving in DICE Flip-Flops at a 22 nm FD SOI Technology Node

Fully Depleted Silicon on Insulator (FD SOI) technology nodes provide better resistance to single event upsets than comparable bulk technologies, but upsets are still likely to occur at nano-scale feature sizes, and additional hardening techniques should be explored. Three flip-flop designs were imp...

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Autors principals: Christopher J. Elash, Zongru Li, Chen Jin, Li Chen, Jiesi Xing, Zhiwu Yang, Shuting Shi
Format: Artigo
Idioma:Inglês
Publicat: MDPI AG 2022-04-01
Col·lecció:Applied Sciences
Matèries:
Dual Interlocked Cell (DICE)
flip-flop
radiation
single event upset
single event effects
soft errors
Accés en línia:https://www.mdpi.com/2076-3417/12/9/4229
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