Analysis of MTJ write circuits and design of hybrid MTJ/CMOS full adder for in-memory computation architecture

Hybrid magnetic tunnel junction/complementary metal oxide semiconductor (MTJ/CMOS) in-memory computation (IMC) has emerged as a future computing architecture that mitigates the memory wall and energy wastage problems observed in the conventional von-Neuman structure. However, the energy consumption...

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Autori principali:	Prashanth Barla, Ramya Moodakare
Natura:	Artigo
Lingua:	Inglês
Pubblicazione:	Taylor & Francis Group 2026-12-01
Serie:	Cogent Engineering
Soggetti:	Magnetic tunnel junction hybrid circuits in-memory computation non-volatile full adder Circuits & Devices Electronic Devices & Materials
Accesso online:	https://www.tandfonline.com/doi/10.1080/23311916.2026.2639225
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