Power Efficient Simple Technique to Convert a Reset-and-Hold Into a True-Sample-and-Hold Using an Auxiliary Output Stage
A technique to implement true-sample-and-hold circuits that hold the output for almost the entire clock cycle without resetting to zero is introduced, alleviating the slew rate requirement on the op-amp. It is based on a Miller op-amp with an auxiliary output stage that increases power dissipation b...
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| Principais autores: | , , , , , |
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| Formato: | Artigo |
| Idioma: | Inglês |
| Publicado em: |
IEEE
2020-01-01
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| coleção: | IEEE Access |
| Assuntos: | |
| Acesso em linha: | https://ieeexplore.ieee.org/document/9055423/ |
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