A BIT-SERIAL ARCHITECTURE FOR A MULTIPLIERLESS DCT
This paper describes the implementation of a multiplierless 1-D DCT which is also applicable to 2-D computation. The key idea is based on the binary DCT of which multipliers are replaced by lifting parameters that essentially are shifts and adds. For lower power applications and smaller hardware siz...
Furkejuvvon:
| Váldodahkkit: | , |
|---|---|
| Materiálatiipa: | Artigo |
| Giella: | Inglês |
| Almmustuhtton: |
UUM Press
2003-05-01
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| Ráidu: | Journal of ICT |
| Fáttát: | |
| Liŋkkat: | https://e-journal.uum.edu.my/index.php/jict/article/view/8017 |
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