Minimal Aliasing Single-Error-Correction Codes for DRAM Reliability Improvement
We discuss the problem of finding a minimal aliasing code among a class of systematic single-error-correction codes that are suitable to be implemented within DRAM die, as opposed to external ECC used in memory controller outside of DRAM chip. We prove a sharp lower bound of aliasing probability and...
Bewaard in:
| Hoofdauteurs: | , , , , , , , |
|---|---|
| Formaat: | Artigo |
| Taal: | Inglês |
| Gepubliceerd in: |
IEEE
2021-01-01
|
| Reeks: | IEEE Access |
| Onderwerpen: | |
| Online toegang: | https://ieeexplore.ieee.org/document/9355147/ |
| Tags: |
Geen labels, Wees de eerste die dit record labelt!
|
