Logical optimization of Boolean nets using Shannon expansion
A synthesis of logical circuits, comprising functional combination blocks of very large scale integration circuits, is one of the most important tasks of computer-aided design. As the data size of design tasks increases, the execution time of synthesis of logic circuits also increases. The global te...
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| Autors principals: | , |
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| Format: | Artigo |
| Idioma: | Russo |
| Publicat: |
National Academy of Sciences of Belarus, the United Institute of Informatics Problems
2019-06-01
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| Col·lecció: | Informatika |
| Matèries: | |
| Accés en línia: | https://inf.grid.by/jour/article/view/658 |
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