Design Methodology of an Equalizer for Unipolar Non Return to Zero Binary Signals in the Presence of Additive White Gaussian Noise Using a Time Delay Neural Network on a Field Programmable Gate Array

This article presents a design methodology for designing an artificial neural network as an equalizer for a binary signal. Firstly, the system is modelled in floating point format using Matlab. Afterward, the design is described for a Field Programmable Gate Array (FPGA) using fixed point format. Th...

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Egile Nagusiak:	Santiago T. Pérez Suárez, Carlos M. Travieso González, Jesús B. Alonso Hernández
Formatua:	Artigo
Hizkuntza:	Inglês
Argitaratua:	MDPI AG 2013-12-01
Saila:	Sensors
Gaiak:	equalizer AWGN neural network FPGA floating point fixed point Matlab Simulink System Generator ISE
Sarrera elektronikoa:	http://www.mdpi.com/1424-8220/13/12/16829
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