Implementation of the block cipher Rijndael using Altera FPGA
A short description of the block cipher Rijndael is presented. Hardware implementation by means of the FPGA (field programmable gate array) technology is evaluated. Im- plementation results compared with other hardware imple- mentations are summarized.
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| Hovedforfatter: | |
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| Format: | Artigo |
| Sprog: | Inglês |
| Udgivet: |
National Institute of Telecommunications
2001-03-01
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| Serier: | Journal of Telecommunications and Information Technology |
| Fag: | |
| Online adgang: | https://jtit.pl/jtit/article/view/35 |
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