On the Feasibility of Implementing a Four-Quadrant CMOS Analog Multiplier Using Only Digital Inverter Standard-Cells as Building Blocks

This work introduces the first four-quadrant CMOS analog multiplier circuit built entirely from digital inverter standard cells, without requiring any analog transistor-sizing methodologies. The multiplication operation is performed using a quadratic cancellation scheme in conjunction with a modifie...

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Autors principals:	Gregorio Zamora-Mejia, Victor H. Carbajal-Gomez, Alejandro Silva-Juarez, Luis C. Alvarez-Simon, Alejandro Diaz-Sanchez, Sergio A. Rosales-Nunez, Julio N. Hernandez-Perez, Rodrigo Jaramillo-Ramirez, Ernesto Conde-Almada, Alejandro I. Bautista-Castillo, Jose M. Rocha-Perez
Format:	Artigo
Idioma:	Inglês
Publicat:	IEEE 2026-01-01
Col·lecció:	IEEE Access
Matèries:	Analog multiplier CMOS four-quadrant inverter gate Nauta’s cell VLSI
Accés en línia:	https://ieeexplore.ieee.org/document/11360980/
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