FPGA Implementations of Feed Forward Neural Network by using Floating Point Hardware Accelerators
This paper documents the research towards the analysis of different solutions to implement a Neural Network architecture on a FPGA design by using floating point accelerators. In particular, two different implementations are investigated: a high level solution to create a neural network on a soft pr...
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| Principais autores: | , , , |
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| Formato: | Artigo |
| Idioma: | Inglês |
| Publicado: |
VSB-Technical University of Ostrava
2014-01-01
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| Series: | Advances in Electrical and Electronic Engineering |
| Assuntos: | |
| Acceso en liña: | http://advances.utc.sk/index.php/AEEE/article/view/831 |
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