A Multiplier-Less Discrete Cosine Transform Architecture Using a Majority Logic-Based Approximate Full Adder
This paper proposes a new approximate full adder (FA) based on the majority logic (ML) concept. The fundamental structure of the ML concept is a 3-input majority voter and is widely utilized in digital arithmetic cells. The ML-based proposed FA works at low power, small delay, and low power-delay-pr...
Enregistré dans:
| Auteurs principaux: | , , |
|---|---|
| Format: | Artigo |
| Langue: | Persa |
| Publié: |
Islamic Azad University Bushehr Branch
2024-03-01
|
| Collection: | مهندسی مخابرات جنوب |
| Sujets: | |
| Accès en ligne: | https://sanad.iau.ir/journal/jce/Article/869992 |
| Tags: |
Pas de tags, Soyez le premier à ajouter un tag!
|
