Exploiting Clock-Slew Dependent Variability in CMOS Digital Circuits Toward Power and EMSCA Resilience

Mathematically secure cryptographic implementations leak critical information in terms of power, EM emanations, etc. Several circuit-level countermeasures are proposed to prevent leakage of the side channel at the source. Circuit-level countermeasures (e.g., IVR, STELLAR, WDDL, etc.) are often prefe...

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Autori principali:	Archisman Ghosh, Md. Abdur Rahman, Debayan Das, Santosh Ghosh, Shreyas Sen
Natura:	Artigo
Lingua:	Inglês
Pubblicazione:	IEEE 2025-01-01
Serie:	IEEE Open Journal of the Solid-State Circuits Society
Soggetti:	AES-256 clock-based countermeasure clock randomization clock-slew correlational power analysis electromagnetic leakage
Accesso online:	https://ieeexplore.ieee.org/document/11165158/
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