Design and Implementation of Decimation Filter for 13-bit Sigma-Delta ADC Based on FPGA
A 13 bit Sigma-Delta ADC for a signal band of 40K Hz is designed in MATLAB Simulink and then implemented using Xilinx system generator tool. The first order Sigma-Delta modulator is designed to work at a signal band of 40 KHz at an oversampling ratio (OSR) of 256 with a sampling frequency of 20.48 M...
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| Materialtyp: | Artigo |
| Språk: | Inglês |
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Tikrit University
2022-03-01
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| Serie: | Tikrit Journal of Engineering Sciences |
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| Länkar: | https://tj-es.com/ojs/index.php/tjes/article/view/293 |
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