Analysis and Design of a Tri-Level Current-Steering DAC With 12-Bit Linearity and Improved Impedance Matching Suitable for CT-ADCs
This paper presents the design of a low-latency, highly linear current-steering DAC for use in continuous-time ADCs. A detailed analysis of equivalent unary-weighted current-steering DAC topologies in terms of mismatch, noise, and output-impedance related distortion is carried out. From this analysi...
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| Principais autores: | , , , , |
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| Formato: | Artigo |
| Idioma: | Inglês |
| Publicado em: |
IEEE
2020-01-01
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| coleção: | IEEE Open Journal of Circuits and Systems |
| Assuntos: | |
| Acesso em linha: | https://ieeexplore.ieee.org/document/9094170/ |
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