Design and simulation of high linearity CMOS analog multiplier
A high linearity CMOS analog multiplier is designed and simulated. The input signal is preprocessed by active attenuator and the CMOS Gilbert multiplier is used for multiplication of the signal, and the bias circuit is designed meanwhile. When the supply voltage is ±1.8 V and the input range is ±0.6...
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| Hlavní autoři: | , , , , , |
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| Médium: | Artigo |
| Jazyk: | Chinês |
| Vydáno: |
National Computer System Engineering Research Institute of China
2020-01-01
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| Edice: | Dianzi Jishu Yingyong |
| Témata: | |
| On-line přístup: | http://www.chinaaet.com/article/3000112389 |
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