Multi‐precision binary multiplier architecture for multi‐precision floating‐point multiplication

Abstract Arithmetic logic units (ALUs) are core components of processing devices that perform required arithmetic and logical operations such as multiplication, division, addition, subtraction, and squaring. The multiplication operation is frequently used in ALUs in engineering applications such as...

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Autors principals:	Geetam Singh Tomar, Marcus Llyode George, Abhineet Singh Tomar
Format:	Artigo
Idioma:	Inglês
Publicat:	Wiley 2021-08-01
Col·lecció:	IET Circuits, Devices and Systems
Matèries:	field programmable gate arrays floating point arithmetic logic design multiplying circuits
Accés en línia:	https://doi.org/10.1049/cds2.12041
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