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Dual Super-Systolic Core for Real-Time Reconstructive Algorithms of High-Resolution Radar/SAR Imaging Systems

A high-speed dual super-systolic core for reconstructive signal processing (SP) operations consists of a double parallel systolic array (SA) machine in which each processing element of the array is also conceptualized as another SA in a bit-level fashion. In this study, we addressed the design of a...

Ausführliche Beschreibung

Gespeichert in:
Hauptverfasser: Javier Vázquez Castillo, Alejandro Castillo Atoche
Format: Artigo
Sprache:Inglês
Veröffentlicht: MDPI AG 2012-02-01
Schriftenreihe:Sensors
Schlagworte:
super-systolic
parallel computing
remote sensing
FPGA
Online-Zugang:http://www.mdpi.com/1424-8220/12/3/2539/
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