Performance evaluation of efficient combinational logic design using nanomaterial electronics
Scaling down trend of CMOS transistor is approaching its lowest point, the rational substitute for the CMOS technology to attain advance improvements in terms of size, low power, and device density usage is an imperative essential. Due to the several physical limitations and circuit bounds of CMOS t...
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| Principais autores: | , , , |
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| Formato: | Artigo |
| Idioma: | Inglês |
| Publicado: |
Taylor & Francis Group
2017-01-01
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| Series: | Cogent Engineering |
| Assuntos: | |
| Acceso en liña: | http://dx.doi.org/10.1080/23311916.2017.1349539 |
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