Energy/Delay Tradeoffs in All-Spin Logic Circuits
All-spin logic (ASL) is a spin-based candidate for implementing logic in the next generation designs. The energy and the delay of ASL circuits are both inherently related to the geometric parameters of ASL gates, and the careful selection of the dimensions for ASL gates is required to achieve optima...
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| Principais autores: | , |
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| Formato: | Artigo |
| Idioma: | Inglês |
| Publicado em: |
IEEE
2016-01-01
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| coleção: | IEEE Journal on Exploratory Solid-State Computational Devices and Circuits |
| Assuntos: | |
| Acesso em linha: | https://ieeexplore.ieee.org/document/7431936/ |
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